Research Article

Secure and Safety-Aware IST Architectures for Next-Gen Automotive Systems

Authors

  • Jayesh Kumar Pandey Independent Researcher, USA

Abstract

Contemporary automotive System-on-Chip architectures necessitate revolutionary transformations in In-System Test implementations to address the convergent requirements of functional safety and cybersecurity protection. Modern vehicle computational platforms integrate multiple subsystems within single-chip solutions while satisfying stringent ISO 26262 compliance standards and emerging cybersecurity regulations. Traditional testing methodologies demonstrate significant inadequacies in protecting against sophisticated cyber threats targeting low-level debug interfaces and test access mechanisms that historically lacked comprehensive security protocols. The evolution toward next-generation automotive systems presents unprecedented design challenges, particularly in implementing robust diagnostic capabilities that maintain operational reliability throughout vehicle lifecycles while preventing unauthorized access to proprietary system data. Secure and safety-aware IST architectures incorporate trusted test controllers, safety-certified Built-In Self-Test engines, hardware-level isolation mechanisms, and secure telemetry systems that collectively address both accidental failures and malicious attacks. Integration complexities arise from fundamental conflicts between safety and security domains, creating substantial barriers through latency considerations, certification gaps, and interoperability challenges across multiple automotive standards. The automotive industry requires comprehensive solutions that implement zero-trust access principles, redundant validation mechanisms, comprehensive audit trails, and cross-functional collaboration between security and functional safety teams. Future advancements encompass AI-driven security policy adaptation, hardware root of trust implementations, digital twin integration for real-time reliability modeling, and distributed validation architectures that enable continuous assessment of system health and safety margins across diverse operational scenarios.

Article information

Journal

Journal of Computer Science and Technology Studies

Volume (Issue)

7 (6)

Pages

897-904

Published

2025-06-23

How to Cite

Jayesh Kumar Pandey. (2025). Secure and Safety-Aware IST Architectures for Next-Gen Automotive Systems. Journal of Computer Science and Technology Studies, 7(6), 897-904. https://doi.org/10.32996/jcsts.2025.7.106

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Keywords:

Secure IST, Functional Safety, Automotive SoCs, ISO 26262, JTAG Security, Runtime Test, Cybersecurity, Self-Test, Digital Diagnostics