AI-Driven Techniques for Power-Optimized and Safety-Critical SoC Design

Abstract

Artificial intelligence is transforming System-on-Chip design, particularly for applications requiring both power efficiency and functional safety. Traditional methodologies face mounting challenges as SoC complexity increases, creating an urgent need for innovative approaches that can navigate extensive design spaces while maintaining safety guarantees. Machine learning techniques throughout the design flow—from architecture exploration to verification—enable sophisticated power optimization without compromising reliability requirements. Deep reinforcement learning optimizes floorplanning while neural networks predict congestion and timing issues early in the process. AI-driven power domain partitioning and dynamic voltage/frequency scaling provide unprecedented control over energy consumption. For safety-critical applications, these techniques incorporate specialized constraints, ensuring fault tolerance while minimizing power overhead. Despite significant advancements, challenges remain in explainability and certification integration, areas where ongoing development continues to bridge the gap between AI-enhanced optimization and safety compliance requirements.